The present invention relates generally to a semiconductor memory device. More particularly, the present invention relates to an address latch circuit of a semiconductor memory device.
In general, a semiconductor memory device serves to perform a basic operation to store and read data. Data input from outside is stored to a cell, which is a storage, in a form of electric signals (HIGH and LOW) by way of a data line. The stored data is read through the reverse path.
The semiconductor memory device is being constantly improved to increase the integration density and operation speed. To raise the operation speed, a synchronous memory device was suggested which operates in synchrony to an external clock given from the outside of the semiconductor memory device. The synchronous memory device uses a single data rate (SDR) scheme which inputs and outputs data in one clock cycle at a data pin in synchrony to a rising edge of the external clock.
By contrast, a double data rate (DDR) synchronous memory device inputs and outputs two data in one clock cycle. That is, two data are input and output at the respective data input and output pins in synchrony to a rising edge and a falling edge of the external clock. Accordingly, the DDR synchronous memory device can have twice the bandwidth of the SDR synchronous memory device.
The DDR synchronous memory devices can be classified to a DDR1 synchronous memory device and a DDR2 synchronous memory device. The DDR1 synchronous memory device performs a 2-bit prefetch at the input and the output, and the DDR2 synchronous memory device performs a 4-bit prefetch at the input and the output under the same condition as the DDR1 synchronous memory device. That is, the DDR1 or DDP2 synchronous memory device consecutively inputs and outputs 2 or 4 data bits synchronized to the clock through input and output ports.
The SDR and the DDR synchronous memory devices support a write latency operation which inputs data after a certain clock cycle after a write command is applied. For instance, when the write latency is 1, after the write command is applied, data is input after one clock cycle. When the write latency is 3, after the write command is applied, data is input after three clock cycles.
However, a conventional semiconductor memory device supporting the write latency operation has the fixed write latency value. When the write latency value is fixed, command bus efficiency of the system is subject to degradation. To overcome this shortcoming, development is underway for a semiconductor memory device that is able to vary write latency.
For instance, the write latency of the DDR2 synchronous memory device is adjustable using a CAS latency and an additive latency which are set by a mode register set at initialization. In detail, the write latency of the DDR2 synchronous memory device is defined as a value acquired by subtracting 1 from a read latency. The read latency is defined as a summation of the CAS latency and the additive latency. Accordingly, the time tRCD is adjustable up to the input time of the write command, to thus achieve command channel flexibility.
FIG. 1 is a block diagram of an address latch circuit 100 of a conventional semiconductor device, and FIG. 2 is an operation timing diagram for illustrating an operation of the address latch circuit of FIG. 1. Specifically, FIG. 2 depicts the operation when the write latency is 1 in the DDR synchronous memory device which operates in the 4-bit prefetch.
Referring now to FIGS. 1 and 2, a latch part 110 of the address latch circuit 100 of the conventional semiconductor memory device latches address signals ADA and ADAZ fed from an address buffer 10 with a command pulse CASP6 and outputs the latched address signal to a clock shift part 120. The clock shift part 120 shifts the latched address signal AT as much as to correspond to the write latency in synchrony to an internal clock CLKP output from a clock buffer 20 and then outputs the shifted address signal to a column address generator 130. The column address generator 130 generates and outputs a column address signal CAT by latching the shifted address signal WL_AT with the write command pulse CASPWT6. The generated column address signal CAT may be fed to a column decoder (not shown) for the decoding.
The generated column address signal CAT is shifted by three clocks based on the internal clock CLKP, compared to the latched address signal AT. This is because the external write command signal WT and the external address signal ADD are input in synchrony to the first rising edge of the external clock CLK from the chip set, whereas four data signals are sequentially input from the second rising edge (because the write latency is 1) of the external clock CLK after the external write command WT is input.
More specifically, all four data signals are input at the fourth rising edge and require about 2-clock time from the fourth rising edge of the external clock CLK for the sake of the delay through a data buffer (not shown) and the arrangement to be used in the semiconductor memory device. Accordingly, to normally process the data in the semiconductor memory device, the generated column address command pulse CASP6 and the latched address signal AT should be shifted up to the sixth rising edge of the external clock CLK.
In other words, the address latch circuit 100 of the conventional semiconductor memory device shifts the address signal AT latched to the rising edge of the column address command pulse CASP6, as much as to correspond to the write latency, and then generates the column address signal CAT by latching it to the rising edge of the write command pulse CASPWT6.
However, when an external clock CLK of short cycle is input, the address latch circuit of the conventional semiconductor memory device is not able to output the column address signal CAT at a required time point for the rapid operation. In detail, when the cycle of the external clock CLK is shortened, the timing of the pulse edge which shifts the address signal may not match and the pulse width, which is the time for logic-processing address signal, may not be ensured.
For instance, given the external clock CLK with 1 GHz frequency, the semiconductor memory device operates in synchrony to the internal clock CLKP having the high pulse width of 500 ps and the low pulse width of 500 ps. In doing so, if the time taken for the semiconductor memory device to shift and logic-process the address signal exceeds 500 ps, the address signal may not be shifted to an intended time point or the logic process of the address signal may be subject to the fail.